SINGLE-EVENT GATE-RUPTURE IN POWER MOSFETS - PREDICTION OF BREAKDOWN BIASES AND EVALUATION OF OXIDE THICKNESS DEPENDENCE

Single-Event Gate-Rupture (SEGR) in Vertical Double Diffused Metal-Oxi de Semiconductor (VDMOS) power transistors exposed to a given heavy io n LET occurs at a critical gate bias that depends on the applied drain bias. A method of predicting the critical gate bias for non-zero drai n biases is presented. The method requires as input the critical gate bias vs. LET for V-DS = OV. The method also predicts SEGR sensitivity to improve for larger gate-oxide thicknesses. All predictions show agr eement with experimental test data.