IMPACT OF OXIDE THICKNESS ON SEGR FAILURE IN VERTICAL POWERMOSFETS - DEVELOPMENT OF A SEMIEMPIRICAL EXPRESSION

This paper investigates the role that the gate oxide thickness (T-OX) plays on the gate and drain failure threshold voltages required to ind uce the onset of single-event gate rupture (SEGR). The impact of gate oxide thickness on SEGR is experimentally determined from vertical pow er metal-oxide semiconductor field-effect transistors (MOSFETs) having identical process and design parameters, except for the gate oxide th ickness. Power MOSFETs from five variants were specially fabricated wi th nominal gate oxide thicknesses of 30, 50, 70, 100, and 150 nm. Devi ces from each variant were characterized to mono-energetic ion beams o f Nickel, Bromine, Iodine, and Gold. Employing different bias conditio ns, failure thresholds for the onset of SEGR were determined for each oxide thickness. Applying these experimental test results, the previou sly published empirical expression [1] is extended to include the effe cts of gate oxide thickness. In addition, observations of ion angle, t emperature, cell geometry, channel conductivity, and curvature at high drain voltages are briefly discussed.