PARALLEL ARCHITECTURES FOR PROCESSING HIGH-SPEED NETWORK SIGNALING PROTOCOLS

Citation
D. Ghosal et al., PARALLEL ARCHITECTURES FOR PROCESSING HIGH-SPEED NETWORK SIGNALING PROTOCOLS, IEEE/ACM transactions on networking, 3(6), 1995, pp. 716-728
Citations number
19
Categorie Soggetti
Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
ISSN journal
10636692
Volume
3
Issue
6
Year of publication
1995
Pages
716 - 728
Database
ISI
SICI code
1063-6692(1995)3:6<716:PAFPHN>2.0.ZU;2-0
Abstract
We study the effectiveness of different parallel architectures for ach ieving the high throughputs and low latencies needed in processing sig naling protocols for high speed networks. A key performance issue is t he trade off between the load balancing gains and the call record mana gement overhead. Arranging processors in large groups potentially yiel ds higher load balancing gains but also incurs higher overhead in main taining consistency among the replicated copies of the cad records. We study this tradeoff and its impact on the design of protocol processi ng systems for two generic classes of parallel architectnres, namely, shared memory and distributed memory architectures. In shared memory a rchitectures, maintaining a common message queue in the shared memory can provide the maximal load balancing gains. We show, however, in ord er to optimize performance it is necessary to organize the processors in small groups since large groups result in higher cad record managem ent overhead In distributed memory architectures with each processor m aintaining its own message queue there is no inherent provision for lo ad balancing, Based on a detailed simulation analysis we show that org anizing the processors into small groups end using a simple distribute d load balancing scheme yields modest performance gains even after cap record management overheads are taken into account, We find that the common message queue architecture outperforms the distributed architec ture in terms of lower response time due to its improved load balancin g capability, Finally, we do a fault-tolerance analysis with respect t o the call-record data structure, Using a simple failure recovery mode l of the processors and the local memory, we show that in the case of shared memory architecture, the availability is also optimized when pr ocessors are organized in small groups, This is because when comparing architectures the higher cap record management overhead incurred for larger group sizes must be accounted for as system unavailability,