POWER DISSIPATION MODELS AND PERFORMANCE IMPROVEMENT TECHNIQUES FOR CMOS INVERTERS WITH RC LINE AND TREE INTERCONNECTIONS

Physical power dissipation models of CMOS inverters with RC line and t ree interconnection networks are presented. Compared to SPICE simulati on results, the maximum error in the model calculated results using th e models is 12% for power dissipation in CMOS inverters with different RC values in each branch of the tree networks, different gate sizes, device parameters, and even input excitation waveforms not deviating m uch from the characteristic waveforms. Based upon the mathematical opt imisation method, as well as on the developed power dissipation models and the delay models, an experimental sizing program is also construc ted for improving various circuit performances such as delay time, pow er-delay product, and delay time with fixed power dissipation specific ations. In this program, given the size of the input logic gate and it s driving interconnection resistances, capacitances, and structures, u sers can choose one improvement technique and determine the suitable s izes and/or number of drivers/repeaters for optimal circuit performanc e. It is found from the sizing results of the experimental CAD program that the required tapering factor for minimum power-delay product in cascaded drivers of interconnection lines or trees is in the range 2-6 instead of 4-8 for a minimum delay. It is also shown that the techniq ue of optimal-size repeaters with cascaded input drivers can lead to t he lowest delay time and power-delay product.