SURFACE PASSIVATION OF THIN SILICON SOLAR-CELLS USING SILICON-ON-INSULATOR WAFER

Solar cells with various cell thicknesses were fabricated using silico n-on-insulator (SOI) wafers, and effects of applied bias voltages (V-b ) at the SOI layer/SiO2 back interface an cell performance were invest igated. A surface passivation effect was obtained by applying negative V-b to accumulate holes at the interface. Both open-circuit voltage ( V-oc) and short-circuit current were improved by applying negative V-b . This effect becomes more dominant for thinner cells. V-oc of 20- and 50-mu m-thick cells at V-b = -15 V increased compared to that of a 10 0-mu m thick cell. Surface recombination velocity (S) was estimated fr om the dependence of internal quantum efficiency on cell thickness. It was found that S decreased from about 10(6) to 10(4) cm s(-1) when V- b changed from 0 to -15 V. The improvement of cell performance by V-b was due to this reduction in S. Therefore, the surface passivation by applying bias voltages is noted as an important technique to realize h igh-efficiency thin silicon solar cells.