HIERARCHY OPTIMIZATION - A MEANS TO ENHANCE EFFICIENCY IN E-BEAM AND OPTICAL LITHOGRAPHY

In the e-beam lithography arena the proximity effect correction (PEG) of large layouts is still regarded as an insurmountable hurdle. The ce ntral processing unit (CPU) time for today's memory layouts (64 Mb) ex tends into weeks and file sizes into Gigabytes. In this paper a new co ncept for hierarchical data handling is introduced, the hierarchy reor ganization. It paves the way for practical applications of very large layouts. Tile initial layout is reorganized according to correction-de pendent criteria. The term hierarchy factor, which is a measure of the compaction of the given hierarchy tree, is introduced. This paper pre sents and explains the theoretical rules of the hierarchy optimization . The problems of hierarchical processing are demonstrated and solutio ns given. The solutions fall into two categories: the first one is com mon to all hierarchical processing, whereas the second one is applicat ion-specific As an example, the hierarchical processing is applied to the proximity effect correction. Scanning electron microscope (SEM) im ages of memory chips are shown by comparing corrected with uncorrected wafers. Files sizes and processing times of all relevant processing s teps ir comparison with flat operation (not exploiting the hierarchy) are given.