The problems in electron beam writing for the membrane-process were in
vestigated; the resist thickness on the thinned membrane was adequatel
y uniform (3 sigma=0.44%), and the resultant pattern size error was ne
gligible. Deformation due to mask chucking onto the electron beam (EB)
cassette was small enough to allow production of acceptable gigabit U
LSI devices. We also confirmed that the SiC membrane is durable enough
for tile task of membrane-process, even with thermal impact of EB ene
rgy 40 times larger than that used in conventional writing. Moreover,
the improvement of pattern size accuracy by using multiple writing was
investigated in detail under various conditions of the beam step size
, the writing time and tile resist sensitivity. The pattern width devi
ation was improved from 20 ro to 13% for 0.15 mu m line-and-space patt
erns by multiple writing, and was little dependent on the beam step si
ze and the resist sensitivity.