NOVEL TITANIUM SALICIDE TECHNOLOGY FOR 0. 25 MU-M DUAL-GATE CMOS

A novel low leakage and low resistance titanium salicide process named ''Silicidation after ion Implantation through the Contamination-Restr ained Oxygen free LPCVD-Nitride layer (SICRON)'' has been developed. I n this method, the impurity ion implantation was performed through nit ride layer to prevent the introduction of recoil oxygen in the silicon film. As a result, the junction leakage current was two orders lower than that of conventional salicide process and low sheet resistance wa s maintained at 0.20 mu m below gate length.