DATA-PATH SYNTHESIS DIGITAL ELECTRONICS .2. BUS SYNTHESIS

Common buses are an extremely efficient structure for achieving area m inimization so that the bus-oriented interconnection of registers and data operators plays an important role in data path synthesis. The ove rriding design goal is efficiently allocating the minimum number of bu ses and gating elements (i.e., multiplexers) for achieving communicati on between the data path elements. New efficient algorithms for the au tomated allocation of buses in data paths have been developed. The ent ire allocation process can be formulated as a graph partitioning probl em This formulation readily lends itself to the use of a varieties of heuristics for solving the allocation problem We present efficient alg orithm which provide excellent solutions to this formulation of the al location problem The operation of the algorithms is clearly demonstrat ed using detailed examples.