CONTROL AND ANALYSIS OF LEAKAGE CURRENTS IN POLY-SI THIN-FILM TRANSISTORS

Control of leakage current in autoregistered columnar and a solid phas e crystallized poly-Si thin-film transistors (TFTs) is discussed. For n-channel TFTs, two parasitic leakage current paths, due to bulk condu ction and back interface conduction, have been identified. It is demon strated that these can be controlled by using sufficiently thin films and by low dose boron back channel implants, respectively. By these me ans, generation limited leakage currents, with values of <4x10(-14) A/ mu m of channel width, have been obtained. The minimum leakage current s, for n- and p-channel TFTs, display the well-known field enhancement which we confirm can be described by phonon assisted tunneling. In we ll-engineered TFTs, with subthreshold slopes of <1 V/dec, we show that the drain fields required to promote the tunneling process are indepe ndent of the trap state density and result entirely from two-dimension al gate-drain coupling effects. Therefore, improving the quality of th e poly-Si will not reduce the exponential dependence of the leakage cu rrent on gate and drain bias, although the absolute value of leakage c urrent will be reduced. (C) 1996 American Institute of Physics.