ON THE NUMBER OF TESTS TO DETECT ALL PATH DELAY FAULTS IN COMBINATIONAL LOGIC-CIRCUITS

The problems involved in handling large numbers of path delay faults w ere alleviated in previous works, by developing fault simulation and t est generation procedures that do not require paths to be explicitly c onsidered. Thus, the methods developed allow the set of all path delay faults to be targeted during test generation and fault simulation. Wi th the problems related to the number of paths removed, a new limiting factor in test generation for path delay faults is revealed, namely, the number of tests required to detect all path delay faults. In this work, the problems related to the number of tests are investigated. A procedure for computing a lower bound on the number of tests is descri bed, and methods for synthesizing circuits with reduced lower bounds o n the numbers of tests are developed. Experimental results are present ed to demonstrate various aspects of the problem.