N(-POLYSILICON GATE PMOSFETS WITH INDIUM-DOPED BURIED-CHANNELS())

In this letter a n(+)-polysilicon gate PMOSFET with indium doped burie d-channel is discussed. The gate length scaling of n(+)-polysilicon ga te buried-length PMOSFET's is limited by the channel punch-through eff ect, Designing shallow counter-doped layers (buried-channels) has been established as a means to reduce the undesirable short channel effect s in these devices [1]-[6], Indium, an acceptor dopant in Si, has a lo w diffusion coefficient and implant statistics favorable for achieving shallow doping layers [7], Indium implants are explored (as an altern ative to BF2) to counter dope the n-tub for adjusting the threshold vo ltage, Devices are fabricated using AT&T's 0.5 mu m CMOS technology [8 ] but with t(ox) = 50 Angstrom. Although no special effort has been ma de to optimize the n-tub or to take full advantage of the diffusion an d implant characteristics of indium, excellent electrical results are obtained for devices with L(eff) = 0.25 mu m. Improved V-th roll-off c haracteristics and reduced body effect (gamma approximate to 0.18 V-1/ 2 versus gamma(B) approximate to 0.40 V-1/2) in indium implanted burie d channels are demonstrated over BF2 implanted buried-channels for PMO SFET's with identical long channel threshold voltages. The effects of incomplete ionization (freeze-out) of the indium acceptor states [9], [10] on the electrical device characteristics will be demonstrated by device simulations and measurements.