MAPPING 3-D IIR DIGITAL-FILTER ONTO SYSTOLIC ARRAYS

We present here an efficient systolic implementation for 3-D IIR digit al filters. The systolic implementation is obtained by using an algebr aic mapping technique. This new mapping technique gives us the choice to mix pipelined variables and broadcast variables. We also determine, through the mapping method, the buffer sizes, the direction of variab les propagations and the data feeding and extracting points. The resul tant systolic array implementation is a modular structure composed of 2-D filter modules connected by simple buffers. This new systolic impl ementation is regular, modular and amenable to VLSI implementation.