METHODS OF SUPPRESSION OR AVOIDANCE OF PARALLEL-PLATE POWER LEAKAGE FROM CONDUCTOR-BACKED TRANSMISSION-LINES

Four useful methods are presented to suppress and/or avoid parallel-pl ate leakage from conductor-backed printed transmission lines, These in clude: 1) the use of shorting-pins; 2) the use of a dielectric-guide-c oupled configuration; 3) using a two-layered conductor-backing configu ration; and 4) dielectric loading on top, New analyses to model the le akage suppression due to the shorting-strips and the dielectric-guide- coupled geometries are presented, with selected demonstrative results and critical discussions, It is concluded that the unwanted leakage in many printed transmission lines, that are otherwise attractive for in tegrated circuits and phased array applications, can be successfully a voided and/or significantly suppressed using the proposed techniques.