A 200-MHZ 15-MW BICMOS SAMPLE-AND-HOLD AMPLIFIER WITH 3 V SUPPLY

A sample-and-hold amplifier designed for the front end of high-speed l ow-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz whi le allowing input/output voltage swings of 1.5 V with a 3-V supply. Th e circuit also incorporates a cancellation technique to relax the trad e-off between the hold-mode feedthrough and the sampling speed, Fabric ated in a 20-GHz 1-mu m BiCMOS technology, an experimental prototype e xhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220 x 150 mu m(2). The measured feedthrough is -5 2 dB for a 50-MHz analog input and the droop rate is 40 mu V/ns.