A 1.8-GHZ CMOS LOW-PHASE-NOISE VOLTAGE-CONTROLLED OSCILLATOR WITH PRESCALER

The implementation of the two high-frequency building blocks for a low -phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-mu m CMOS process is discussed, The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power, The design of these bo ndwire inductors is discussed in great detail, A general formula for t he theoretical limit of the phase noise of LC-tuned oscillators is pre sented. The design of a special LC-tank allows a trade-off between noi se and power, The realized VCO has a phase noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply, The prescaler has a fixed division ratio of 128 and uses an enhanced ECL- alike high-frequency D-flipflop, Its power consumption is 28 mW.