A SINGLE-CHIP 900 MHZ CMOS RECEIVER FRONT-END WITH A HIGH-PERFORMANCELOW-IF TOPOLOGY

An analog receiver front-end chip realized in a 0.7 mu m CMOS technolo gy is presented, It uses a new, high performance, downconverter topolo gy, called double quadrature downconverter, that achieves a phase accu racy of less than 0.30 in a large passband around 900 MHz, without req uiring any external component or any tuning or trimming, A high perfor mance low IF receiver topology is developed with this double quadratur e downconverter. The proposed low-IF receiver combines the advantages of both the classical IF receiver and the zero-IF receiver: an excelle nt performance and a very high degree of integration, In this way, it becomes possible to realize a true fully integrated receiver front-end that does not require a single external component and which is, diffe rent from the zero-IF receiver, nonetheless totally insensitive to par asitic baseband signals and self-mixing products.