3.5-GB SX4-CH SI BIPOLAR LSIS FOR OPTICAL INTERCONNECTIONS/

The 3.5-Gb/s, 4-ch transmitter and receiver LSI's described here inclu de a 5-to-1 multiplexer, a 1-to-5 demultiplexer, and analog PLL circui ts that can generate high-speed clock (3.5 GHz) and retimed data, The chips make it possible to connect twenty pairs of 700-Mb/s electrical ports (14-Gb/s throughput) without any external elements even for the PLL, Both the transmitter and receiver LSI are 4.5-mm-square and are f abricated by a 40-GHz 0.5-mu m Si bipolar process, The transmitter LSI dissipates 2.5 W, and the receiver LSI dissipates 3.6 W, Both have -4 .5- and -2-V supply voltages.