This paper presents 8-tap and 10-tap, 6-b filters designed to provide
PR-IV channel equalization at data rates in excess of 20 megabyte/s, A
chieving high sampling rates while reducing power and area required an
optimized distributed arithmetic (DA) architecture combined with cust
om circuit design and layout, These filters improve attainable data ra
te by 40% while reducing macro area by 20% compared with standard-cell
-designed filters using the same architecture and technology.