A CMOS GATE ARRAY WITH 600 MB S SIMULTANEOUS BIDIRECTIONAL I/O CIRCUITS/

A 610 kG gate array with simultaneous bidirectional I/O circuits has b een developed using 0.5 mu m CMOS four metal layer process technology. The number of I/O circuits is 608. A digitally-impedance-controlled l ow voltage swing output buffer circuit achieves high data throughput a nd low power, The maximum effective communication bandwidth is 600 Mb/ s per pin, and the average power consumption of the I/O circuits is 12 mW per pin, A PLL can create the proper clock edge timing to latch da ta of 300 Mb/s with 120 ps of peak-to-peak jitter, Wide data band widt h can be obtained using a 1000 pin-class package for parallel processo r systems.