FORMAL SYNTHESIS OF VLSI LAYOUTS FROM ALGORITHMIC SPECIFICATIONS

Due to advances in VLSI technology, it is possible to implement comple x digital systems on a single chip. However modelling such large and c omplex systems at structural level is tedious and error prone. This fa ct has motivated the development of several high-level synthesis syste ms. The process consists of translating the abstract behavioural repre sentation generally at the algorithmic level into a structural realiza ble representation. In this paper we present a formal approach for hig h-level synthesis. This formal high-level synthesis system uses mu-rec ursive algorithms to model the behaviour to be synthesized. These algo rithms can be mathematically verified for correctness before being sub jected to the task of translation. As a case study, the modelling and synthesis of VLSI layouts for matrix-matrix multipliers is discussed.