ISSUES IN THE DESIGN OF A LOGIC SIMULATOR - ELEMENT MODELING FOR EFFICIENCY

Authors
BROWN AD NICHOLS KG ZWOLINSKI M
Citation
Ad. Brown et al., ISSUES IN THE DESIGN OF A LOGIC SIMULATOR - ELEMENT MODELING FOR EFFICIENCY, IEE proceedings. Circuits, devices and systems, 143(1), 1996, pp. 21-27
Citations number
12
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEE proceedings. Circuits, devices and systems → ACNP
ISSN journal
13502409
Volume
143
Issue
1
Year of publication
1996
Pages
21 - 27
Database
ISI
SICI code
1350-2409(1996)143:1<21:IITDOA>2.0.ZU;2-B
Abstract
A unique method of using inertial cancellation in the detection of set -up and hold-time violations in flip-flops and other memory-like eleme nts is described, together with an effective technique of modelling so urces so that each queues at most one event at any time. Results are p resented showing a test circuit failing to operate correctly as a resu lt of timing violations, correctly simulated by these modelling techni ques.