HIGH-SPEED PERFORMANCE OF 0.35 MU-M CMOS GATES FABRICATED ON LOW-DOSESIMOX SUBSTRATES WITH WITHOUT AN N-WELL UNDERNEATH THE BURIED OXIDE LAYER

We present experimental results concerning the propagation delay time of the 0.35 mu m CMOS gate chains (inverter, 3NAND, and 3NOR) fabricat ed on low-dose SIMOX substrates with and without the N-well formed und erneath the buried oxide layer in the PMOS region, Using such experime ntal data as the capacitance voltage characteristics of the buried oxi de layer, and the enhanced PMOS transistor drivability due to the nega tive back bias effect, we clarify the most essential factor of the hig h-speed performance of the CMOS/SIMOX circuits fabricated on a low-dos e SIMOX substrate.