ACCELERATED REVERSE EMITTER-BASE BIAS STRESS METHODOLOGIES AND TIME-TO-FAILURE APPLICATION

A second current-acceleration method for measuring the reliability of silicon bipolar transistors under reverse emitter-base bias stress is demonstrated in this paper. The low-voltage operation condition in sub micron transistors may be attained during the stress experiments, prov iding an accurate determination of the transistor's operation time-to- failure (TTF) without extrapolating from higher voltage stress data, T wo different current-acceleration stress methods are demonstrated in o ne transistor design and compared with the traditional voltage-acceler ation method using the carrier kinetic energy as the independent varia ble, It is shown that the traditional voltage-acceleration method can give an erroneous and larger extrapolated time-to-failure by several o rders of magnitude in some devices.