MODELING AND EXTRACTION OF INTERCONNECT CAPACITANCES FOR MULTILAYER VLSI CIRCUITS

We report an accurate and practical method of estimating interconnect capacitances for a given circuit layout. The method allows extraction of the complete circuit level capacitances at each node in the circuit . The layout geometry is reduced into base elements that consist of di fferent vertical profiles at each node in the layout. Accurate analyti cal models are developed for calculating capacitances of multilayer st ructures using a 2-D capacitance simulator TDTL. These models are then transformed into 3-D geometry. The resulting model capacitance values are found to be within 10% of both the measured data and 3-D simulati ons of structures that are prevalent in a typical VLSI chips. The mode ls and their coefficients for different vertical profiles are stored i n the capacitance extraction tool CUP, which is coupled to the layout extractor HILEX. As each base element has a unique vertical profile, t he corresponding capacitance can easily be calculated for each node th at is then written out to a circuit netlist. The comparisons of the mo dels with the measured data, as well as 3-D simulations results, are a lso discussed.