COD - ALTERNATIVE ARCHITECTURES FOR HIGH-SPEED PACKET-SWITCHING

Current architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to u tilize recent advances in photonic technology in order to enable highe r speed operation. In this paper, we introduce cascaded optical delay line (COD) architectures for ultra high speed packet switching. The CO D architectures utilize an extremely simple distributed electronic con trol algorithm to configure the states of 2 x 2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessa ry. The simplicity of the architectures may also make them suitable fo r ''lightweight'' all-electronic implementations. For optical implemen tations, the number of 2 x 2 photonic switches used is a significant f actor determining cost. We present a ''baseline'' architecture for a 2 x 2 buffered packet switch that is work conserving (i.e. nonidling) a nd has the first-in, first-out (FIFO) property. If the arrival process es are independent and without memory, the maximum utilization factor is rho, and the maximum acceptable packet loss probability is epsilon, then the required number of 2 x 2 photonic switches is O(log (epsilon )/log (gamma)), where gamma = rho(2)/(rho(2) + 4 - 4 rho). If we modif y the baseline architecture by changing the delay line lengths then th e system is no longer work conserving and loses the FIFO property, but the required number of 2 x 2 photonic switches is reduced to O(log [l og (epsilon)/log (gamma)]). The required number of 2 x 2 photonic swit ches is essentially insensitive to the distribution of packet arrivals , but long delay Lines are required for bursty traffic.