ANALOG VLSI IMPLEMENTATION FOR STEREO CORRESPONDENCE BETWEEN 2-D IMAGES

Many robotics and navigation systems utilizing stereopsis to determine depth have rigid size and power constraints and require direct physic al implementation of the stereo algorithm. The main challenges lie in managing the communication between image sensor and image processor ar rays, and in parallelizing the computation to determine stereo corresp ondence between image pixels in real-time. This paper describes the fi rst comprehensive system level demonstration of a dedicated low-power analog VLSI (very large scale integration) architecture for stereo cor respondence suitable for real-time implementation. The inputs to the i mplemented chip are the ordered pixels from a stereo image pair, and t he output is a two-dimensional disparity map. The approach combines bi ologically inspired silicon modeling with the necessary interfacing op tions for a complete practical solution that can be built with current ly available technology in a compact package. Furthermore, the strateg y employed considers multiple factors that may degrade performance, in cluding the spatial correlations in images and the inherent accuracy l imitations of analog hardware, and augments the design with countermea sures.