CIRCUIT PARTITIONING VIA SET PARTITIONING AND COLUMN GENERATION

In this paper, a new application of the methodology of set partitionin g formulation augmented with heuristic column generation is presented. An efficient method for the partitioning of large-scale electronic ci rcuits is developed based on this methodology. Circuit partitioning co nstitutes a major step of the physical design phase of electronic circ uits, the fundamental components of electronic products. The major adv antage of the scheme presented here is to provide a framework for an e ffective integration of most existing circuit partitioning methods. An other attractive feature of the current approach is the incorporation of interactive optimization: The circuit designer controls the operati on of the procedure and enhances its performance by suggesting and/or requiring specific partitions. Following the development of the model, the solution approach is presented and computational results are repo rted for several benchmark circuits.