SI-SIO2 ELECTRONIC INTERFACE ROUGHNESS AS A CONSEQUENCE OF SI-SIO2 TOPOGRAPHIC INTERFACE ROUGHNESS

Numerical calculations were used to assess the probable microscopic di stribution of the electric field along or close to the actual Si-SiO2 interface of a metal oxide semiconductor (MOS) capacitor biased into a ccumulation. Silicon wafers were oxidized to 20 nm at 1150 degrees C b y rapid thermal oxidation, according to two different thermal recipes in order to yield different Si-SiO2 interface roughnesses. After oxide removal, typical atomic force microscopy (AFM) line scans of the sili con surface were exported into the MEDICI program as a description of the Si-SiO2 interface in order to calculate the electric field distrib ution within the oxide layer of a bidimensional MOS capacitor biased i nto accumulation. This distribution was found to be highly inhomogeneo us even for relatively smooth Si-SiO2 interfaces, displaying strong lo cal electric field enhancements, the spatial distribution of which wil l be called electronic roughness in this work. Simple local oxide thin ning at the position of the protrusions cannot account for these field enhancements, thus indicating that the shape of the protrusion is dic tating the electronic roughness. The electronic roughness could be cor related with electric breakdown characteristics of actual MOS capacito rs prepared on these wafers.