SINGLE-CHIP IMPLEMENTATION OF MPEG2 DECODER FOR HDTV LEVEL PICTURES

A single chip MPEG2 MP@HL video decoder has been developed. which cons ists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip fra me memories and the interfaces associated with it. Owing to sophistica ted I/O interfaces among functional units, the macroblock level pipeli ne in conjunction with different decoding facilities attains a high th roughput to such an extent as to decode HDTV images in real time. More over, a set of these functional units, pipeline buffers, and frame mem ory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8 x 9. 2 mm(2) with a 0.6 mu m triple-metal CMOS technology, and dissipates 1 .2 W from a single 3.3 V supply.