AN INSULATED GATE BIPOLAR-TRANSISTOR WITH HIGH SURGE ENDURANCE

The relationship between the device property under drain-source breakd own and device structure parameters of insulated gate bipolar transist ors was simulated. Then the following facts were revealed: 1 the impur ity concentration in the n(-) drain layer and the layer thickness dete rmine the breakdown mode. One such mode is the avalanche-suppressed pu nch-through mode proposed by the authors, where the depletion layer in the n(-) drain layer reaches the p drain substrate and breakdown is caused by the hole injection from the p(+) drain substrate to the n(-) drain layer. Another mode is the nonpunch-through mode, where avalanc he takes place in the neighborhood of the junction between the p body layer and n drain layer, causing breakdown; 2 the breakdown energy spr eads more and the hot carrier concentration near the device surface is lower in the avalanche-suppressed insulated gate bipolar transistor t han in the nonpunch-through insulated gate bipolar transistor. As a re sult, the breakdown resistance of the former transistor is higher than that of the latter transistor; and 3 it was found that the breakdown voltage is more stable against the changes in the drain current and te mperature in the former transistor than in the latter transistor. It w as found also that the former transistor has a higher surge energy end urance than the latter transistor.