ANALYSIS OF MECHANISMS FOR HOT-CARRIER-INDUCED VLSI CIRCUIT DEGRADATION

In this paper we discuss in detail the mechanism for hot-carrier induc ed circuit degradation in actual 64Mb DRAM (dynamic random access memo ry), by investigating the DRAM specification parameter shift due to tr ansistor aging in each of the constituent circuits. It was found that hot-carrier induced transistor aging of the circuit block does not dir ectly affect the internal clock speed degradation, however, it does gr eatly reduces the design margin of a circuit which suffers from heavy loads. In addition, an in-depth study of the dynamic hot-carrier degra dation behavior of N-channel transistors more common in actual VLSI ci rcuits was carried out based on the alternating stress and charge pump ing techniques.