STRESS EFFECT ON THE RELIABILITY OF PMOS TFTS FOR 16 MB SRAM - DC STRESS AT ROOM AND ELEVATED-TEMPERATURES

The present a systematic experimental study of the electrical stress e ffects in p-channel metal-oxide-semiconductor thin film transistors (p MOS TFTs) used as active loads in high density static random access me mory (SRAM) circuits. Specifically, the effects: of de stresses occurr ing during standby were investigated in devices both with and without offset and at room and elevated substrate temperatures. The stresses a ssociated with the OFF regime biases give rise to a drastic reduction of leakage current and at the same time, a significant increase in the ON current. These effects are particularly pronounced in devices with out offset and for stress biases applied at room temperature or below. Although at elevated substrate temperature the leakage current itself is enhanced by a few orders of magnitude the stress-induced parameter shifts are shown to be smaller than those at lower temperatures. Addi tionally, the stress induced reliability aspects of pMOS TFTs used for a Mb and 16 Mb SRAM are compared and discussed.