SELF-ALIGNED OFFSET-GATED POLY-SI TFTS WITH SYMMETRICAL SOURCE DRAIN CHARACTERISTICS

We propose a new fabrication process for poly-Si thin film transistors in order to reduce leakage-current with a self-aligned offset-gated s tructure by employing a photo-resist reflow process. The new fabricati on method makes the gate-oxide over the offset region with the assista nce of sub-gate and reflowed photoresist. The new method does not requ ire any additional offset mask step and the self-aligned implantation is applicable so that poly-Si TFT with the symmetrical offset length i s easily fabricated. A symmetrical offset length from 0.7 mu m to 2.3 mu m is obtained successfully. The experimental results show that the maximum ON/OFF ratio is obtained with a considerable reduction in leak age-current when the offset length is 1.1 mu m.