OPTICALLY INTERCONNECTED KOHONEN NET FOR PATTERN-RECOGNITION

The test chip of optically interconnected Kohonen net which realizes t he parallel pattern recognition was designed and fabricated. The optic al waveguides, micromirrors and photodiodes were integrated on a Si wa fer and complementary metal oxide semiconductor (CMOS) chips were bond ed on the same Si wafer. The optical input data are distributed to the CMOS circuits by the branched waveguide and the distances between the input and the reference data are calculated. This test circuit operat ed at a frequency of 6.7 MHz.