A JOSEPHSON BUILT-IN SELF-TESTING (JBIST) SYSTEM FOR GIGAHERTZ FUNCTIONAL TESTS OF JOSEPHSON RAMS

We propose a Josephson built-in self-testing (JBIST) system. The aim o f the JBIST system is to perform functional tests for Josephson RAMs a t more than 1 GHz. The prototype JBIST circuit is designed for a 256 b it Josephson RAM, and consists of an instruction ROM and a processing circuit. A MARCHING test program is written into the instruction ROM, and the processing circuit executes the program on the instruction ROM . Total power consumption of the JBIST circuit is designed to be 4.2 m W. Estimated delays for the critical paths suggest the potential of a gigahertz clock testing. We fabricated the JBIST circuit chips by usin g Nb-AIO(x)-Nb Josephson junctions. The component circuits in the JBIS T circuit (sequence controller, comparator, and instruction ROM) are s uccessfully operated.