EVALUATION OF SOFT-ERROR IMMUNITY FOR 1-V CMOS MEMORY CELLS WITH MTCMOS TECHNOLOGY

Soft-error immunity of a l-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a mul ti-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circu it combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A l-kb me mory was designed and fabricated with 0.5-mu m MTCMOS technology and t he soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at I-V operations.