HALF-V-CC PLATE NONVOLATILE DRAMS WITH FERROELECTRIC CAPACITORS

An architecture for a high-density nonvolatile memory with ferroelectr ic capacitors is proposed and simulated. The architecture includes: (1 ) the operation procedure for DRAM-like memory cells with a V-cc/2 com mon plate, (2) commands and pin arrangement compatible with those of D RAMs. The resulting ferroelectric memory is expected to show, in addit ion to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handl ed in the same way as DRAMs. The proposed basic operations are confirm ed by using circuit simulations, in which an equivalent circuit model for ferroelectric capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with pol arization switching. Designing the reference-voltage generator for 1T1 C (one-transistor and one-capacitor) cells, while considering signal r eduction along with fatigue, will be another issue for achieving high- density comparable to that of DRAMs.