A DISTRIBUTED GLOBALLY REPLACEABLE REDUNDANCY SCHEME FOR SUB-HALF-MICRON ULSI MEMORIES AND BEYOND

This paper describes a distributed globally replaceable redundancy (DG R) scheme which achieves a higher optimization of the trade-off betwee n yield enhancement and chip area penalty, A newly developed yield sim ulator using the Monte Carlo method has estimated the effectiveness of the DGR scheme in a quantitative manner. The new redundancy scheme is expected to enhance the yield by several times compared with conventi onal redundancy in the early stages of production, The DGR scheme has been successfully implemented in an experimental 4 Mb SRAM with a 3.0% area overhead and an average redundancy usage efficiency of 61% has b een obtained in repaired pass chips.