ANALYSIS AND OPTIMIZATION OF SERIES-GATED CML AND ECL HIGH-SPEED BIPOLAR CIRCUITS

An analytical model for calculating the propagation delay time of two- level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented, The analytical delay m odel accounts for all the device parasitics and the device sizes of th e two levels, Moreover, high-current effects are also considered in th e developed model, Exploiting these two features, the model has been s uccessfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits for maximum speed (minimum delay), A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model.