ALL-N-LOGIC HIGH-SPEED TRUE-SINGLE-PHASE DYNAMIC CMOS LOGIC

In this paper, a novel all-N-logic single-phase high speed dynamic CMO S logic is introduced and analyzed, The circuits achieve high speed by eliminating the need for the low-speed P-logic blocks, The use of all -N-logic allows the speed of the proposed circuits to be two to three times the speed of conventional CMOS dynamic circuits. An 2:1 frequenc y divider, using proposed ANL2 circuits, is simulated using 0.8 mu m C MOS technology,vith the operating clock frequency reaching as high as 1.5 GHz, A pipelined 8-b carry generator of five-stacked NMOS transist ors, which operates at a clock rate of over 710 MHz, has also been sim ulated, Experimental results show that the proposed circuits operate o ver 910 MHz implemented in a 1.2 mu m CMOS technology.