HIGH-SPEED, HIGH LINEARITY CMOS BUFFER AMPLIFIER

Citation
T. Saether et al., HIGH-SPEED, HIGH LINEARITY CMOS BUFFER AMPLIFIER, IEEE journal of solid-state circuits, 31(2), 1996, pp. 255-258
Citations number
9
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
00189200
Volume
31
Issue
2
Year of publication
1996
Pages
255 - 258
Database
ISI
SICI code
0018-9200(1996)31:2<255:HHLCBA>2.0.ZU;2-F
Abstract
A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 mu m double-polysilicon double-metal CMOS technology and has o n-chip frequency compensating capacitors. The basic performance factor s obtained in this design are: A(o) = 70 dB, GBW = 5.5 MHz, SR = 7 V/m u s, and upsilon(R) = 10nV/root Hz@100 kHz. With a supply voltage of /-5 V, the amplifier has a +/-4.7 V output swing and features a low 30 Omega open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V(out.pp) output level with the fundamental frequ ency of 20 kHz. From the test results, it is demonstrated that an over all high performance is achieved with this design.