ON THE THRESHOLD VOLTAGE AND CHANNEL CONDUCTANCE OF POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS

A model for the grain-boundary barrier height of undoped polycrystalli ne silicon thin-film transistors is developed based on a rodlike struc ture of the grains with a square cross section and a Gaussian energy d istribution of the trapping states at the grain boundaries. An analyti cal expression for the threshold voltage is derived in terms of the di stribution parameters of the grain-boundary trapping states, the grain size, and the gate oxide thickness. Comparison between the developed model and the experimental drain current versus gate voltage data has been made and excellent agreement was obtained. The key parameters aff ecting the threshold voltage and the channel conductance of the transi stor were investigated by computer stimulation. The threshold voltage is mainly affected by the grain size and the gate oxide thickness. For the improvement of the channel conductance, besides the passivation o f the grain-boundary trapping states, the increase of the grain size a nd mainly the scaling down of the gate oxide thickness are the key fac tors. (C) 1996 American Institute of Physics.