FLOATING-POINT ADDER SUBTRACTOR PERFORMING IEEE ROUNDING AND ADDITION/SUBTRACTION IN PARALLEL/

A model for the floating point adder/subtracter which can perform roun ding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described a nd algebraically verified. Processing flow of the conventional Roaring point addition/subtraction operation consists of alignment, addition/ subtraction, normalization, and rounding stages. In general, the round ing stage requires a high speed adder for increment, increasing the ov erall execution time and occupying a large amount of chip area. Furthe rmore, it accompanies additional execution time and hardware logics fo r renormalization stage which may occur by an overflow from the roundi ng operation. A floating adder/subtracter performing addition/subtract ion and IEEE rounding in parallel is designed by optimizing the operat ional flow of floating point addition/subtraction operation. The float ing point adder/subtracter presented does not require any additional e xecution time nor any high speed adder for rounding operation. In addi tion, the renormalization step is not required because the rounding st ep is performed prior to the normalization operation. Thus, performanc e improvement and cost-effective design can be achieved by this approa ch.