A SUPPLEMENTARY SCHEME FOR REDUCING CACHE ACCESS TIME

Among three factors mainly affecting the cache access time, i.e., hit access time, miss rate and miss penalty, previous approaches were focu sed on reducing the hit access time and miss rate. In this paper, we p ropose a scheme called MPC (Miss-Predicting Cache) which achieves addi tional reduction of the average instruction cache access time through reducing the miss penalty. The MPC scheme which predicts cache miss an d starts cache miss operations in advance, therefore, is supplementary to previous cache schemes targeted for reducing the miss rate and/or hit access time. Performance of the MPC scheme was evaluated using din ero, a trace-driven cache simulator, with the estimation of silicon ar ea using 0.8 mu m CMOS standard cell library.