ACCELERATED TESTING FOR COSMIC SOFT ERROR RATE

This paper describes the experimental techniques which have been devel oped at IBM to determine the sensitivity of electronic circuits to cos mic rays at sea level, It relates IBM circuit design and modeling, chi p manufacture with process variations, and chip testing for SER sensit ivity, This vertical integration from design to final test and with fe edback to design allows a complete picture of LSI sensitivity to cosmi c rays, Since advanced computers are designed with LSI chips long befo re the chips have been fabricated, and the system architecture is full y formed before the first chips are functional, it is essential to est ablish the chip reliability as early as possible, This paper establish es techniques to test chips that are only partly functional (e,g,, onl y 1Mb of a 16Mb memory may be working) and can establish chip soft-err or upset rates before final chip manufacturing begins, Simple relation ships derived from measurement of more than 80 different chips manufac tured over 20 years allow total cosmic soft-error rate (SER) to be est imated after only limited testing, Comparisons between these accelerat ed test results and similar tests determined by ''field testing'' (whi ch may require a year or more of testing after manufacturing begins) s how that our experimental techniques are accurate to a factor of 2.