A DECISION CIRCUIT WITH PHASE-DETECTORS FOR 10-GB S OPTICAL COMMUNICATION-SYSTEMS/

A decision circuit with a function of detecting the phase difference b etween input data and clock signal is presented. Direct coupled FET lo gic (DCFL) was used for basic gates. The circuit architecture was chos en to be suitable for DCFL. Novel circuit technologies were adopted to the phase detectors. InGaAs/AlGaAs pseudomorphic inverted HEMT's were used for fabrication. The decision circuit showed a wide phase margin of 288 degrees and small decision ambiguity of 27 mV(PP) up to 10 Gb/ s. Linear and wide-range phase detection was achieved as well as an ab ility to compensate the variation of transition density, input bias an d temperature.