This paper describes a new active pull-up (APU) interface for high-spe
ed point-to-point transmission. The APU circuit is used to speed up a
low-power-consumption open-drain-type interface. It pulls up the outpu
t at a fixed duration and this limiting of the pull-up duration preven
ts the pull-up operation from going into a counter phase at over 1-Gbp
s operation. Measurements of test chips fabricated with 0.25-mu m bulk
CMOS show 1.7-Gbps error-free operation for the APU interface and 1.2
-Gbps operation for the open-drain-type interface: The APU interface i
s 1.4 faster than the open-drain type. The application of a 0.25-mu m
SIMOX-CMOS device to the APU interface increases the bit rate 1.5 time
s compared with 0.25-mu m bulk CMOS. Altogether the interface covers t
he bit rate of 2.4 Gbps, which is a layer of the communication hierarc
hy. The APU interface circuit can be applied to large-pin-count LSIs b
ecause of its full-CMOS single-rail structure.