MEASUREMENT OF TRANSIENT EFFECTS IN SOI DRAM SRAM ACCESS TRANSISTORS/

Bitline-induced transient effects in access transistors pose a problem in SOI DRAM and SRAM cells, The floating-body potential is affected b y the bitline so changes in the bitline potential may upset the charge stored in the memory cell, Transient effects in SOI access transistor s are measured versus the time the bitline is at high voltage, and V-D D for fully- and partially-depleted SOI devices, Bulk devices show no bitline-induced transient effects, Measurements show that the magnitud e of the charge upset can be large enough to disturb the charge stored in DRAM and SRAM cells.,Measurements also show that for any substanti al upsets to occur, the time the bitline has to be at high voltage is on the order of milliseconds, Although the effect of bitline transitio ns is cumulative, the amount of charge upset when the bitline switches rapidly (i.e., much less than millisecond periods) is shown to be neg ligible, Thus, proper design of SRAM upset-charge protection and DRAM refresh time should circumvent this problem.