PARALLEL DFT COMPUTATION ON BIT-SERIAL SYSTOLIC PROCESSOR ARRAYS

The paper shows how novel one-dimensional and two-dimensional systolic processing architectures, comprising up to N coordinate rotation digi tal computer (CORDIC) processing elements (PEs), can be used to carry out hardware-efficient parallel implementations of the N-point discret e Fourier transform (DFT), offering highly attractive throughput rates in relation to the conventional N-processor linear systolic array. Th e CORDIC PE is implemented in bit-serial form using single-bit half-ad der (HA) and full-adder (FA) circuits. It is thus extremely efficient, in terms of speed/area product and possesses simple interconnects, fa cilitating the mapping of potentially thousands of such units onto a s ingle chip.